The present invention generally pertains to current regulation in integrated circuits and is particularly directed to the regulation of current through depletion devices in a MOS integrated circuit containing a plurality of depletion devices on a common substrate.
In designing a MOS integrated circuit to operate at a certain maximum amount of power and at a certain minimum frequency, the most important parameter is the depletion device current variation. The power that must be specified is directly proportional to the maximum current through the depletion devices.
Also, in certain circuit applications, depletion devices are required to conduct at least a minimum amount of current to enable conduction in circuit devices connected thereto. For example in an integrated circuit in which a pair of depletion devices are both series-coupled and cross-coupled to a pair of enhancement devices to define a cross-coupled latch, such as in an NMOS static RAM memory cell, the depletion devices must conduct at least a minimum amount of current to enable the enhancement device that is cross-coupled thereto to conduct the amount of current that is required for the storage of information. In such integrated circuits the depletion devices and enhancement devices are all fabricated on a common substrate; and the circuit contains both a plurality of given depletion devices having a given size and a given pinch-off voltage characteristic and a plurality of given enhancement devices having a given size and a given threshold voltage characteristic.
By regulating the current through the given depletion devices to provide only a tight current variation above the minimum current required, the power specification is reduced, which in turn enhances the speed/power specification for the integrated circuit.